The present invention relates generally to Phase Change Memory (PCM) cells and programming methods and more particularly to an improved system and method for more efficiently programming bits in multilevel PCM cells to mitigate drift.
A Phase Change Memory (PCM) cell includes a memory element of a phase change material having a first state, in which the phase change material is fully crystalline and has a minimum resistance level, a second state in which the phase change material is fully amorphous and has a maximum resistance level, and a plurality of intermediate states, in which the phase change material includes a mixture of both crystalline regions and amorphous regions having intermediate resistance values. As referred to herein, a cell or phase change material cell is any 2-dimensional or 3-dimensional structure that is formed of or includes a portion of phase change material. PCM materials include Chalcogenides which group of materials contain a chalcogen (Periodic Table Group 16/VIA) and another element. Selenium (Se) and tellurium (Te) are the two most common elements in the group used to produce a chalcogenide semiconductor when creating a phase change memory cell. An example of this would be Ge2Sb2Te5 (GST), SbTe, and In2Se3.
As known, the amorphous phase of a PCM tends to have high electrical resistivity, while the crystalline phase exhibits a low resistivity, e.g., orders of magnitude lower. Due to this large resistance contrast, the change in sensing signal between fully crystalline state and fully amorphous state is quite large, permitting for the immediate multiple analog levels needed for multi-level cell (MLC) operations.
In a PCM cell reset operation, a larger electrical current is applied in order to melt the central portion of the cell, and if this pulse is terminated abruptly, the molten material quenches into the amorphous phase, producing a cell in the high-resistance state. The reset operation tends to be fairly current and power hungry, and thus care must be taken to choose an access device capable of delivering high current and power without requiring a significantly larger footprint than the PCM element itself.
Typical semiconductor computer memories are fabricated on semiconductor substrates consisting of arrays of large number of physical memory cells. In general, one bit of binary data is represented as a variation of a physical or electrical parameter associated with a memory cell. Commonly used physical/electrical parameters include a threshold voltage, Vth, variation of Metal Oxide Field Effect Transistor (MOSFET) due to the amount of charge stored in a floating gate or a trap layer in nonvolatile Electrically Erasable Programmable Read Only Memory (EEPROM), or resistance variation of the phase change element in Phase-change Random Access Memory (PRAM).
Increasing the number of bits to be stored in a single physical semiconductor memory cell is an effective method to lower the manufacturing cost per bit. Multiple bits of data can also be stored in a single memory cell when variations of the physical parameter can be associated with multiple bit values. This multiple bits storage memory cell is commonly known as a Multi-Level Cell (MLC). Significant amount of effort in computer memory device and circuit designs is devoted to maximize the number of bits to be stored in a single physical memory cell. This is particularly true with storage class memory, e.g., non-volatile Flash memories commonly used as mass storage devices.
FIG. 2 depicts an example PCM cell 25 and a programming (e.g., write operation)/sensing (read operation) in an apparatus for performing read and write operations. Typically, an apparatus can program a PCM cell, for example, by a programmed current pulse applied through PCM cell 25 and a control access device (e.g., a transistor device) 30, e.g., a CMOS FET device. From known physical relatiuons, resistance R is determined by fraction of amorphous size, amorphous material properties including trap states distribution, density, etc. and applied voltage V to the PCM cell 25.
In FIG. 2, the PCM cell 25 includes a bit line terminal 28 receiving programming voltage V. One transistor terminal (e.g., source or drain) of FET 30 connects the PCM cell at a second PCM or WL terminal. A gate of FET 30 provides a second PCM cell or wordline (WL) terminal 32 and connects to a wordline conductor WL. A third terminal of the FET device 30 (e.g., drain or source) is shown connected to a ground or neutral. In one embodiment, voltage present at the wordline (WL) terminal 32 in the manner as shown in FIG. 3B, configures the control access device, e.g., FET transistor 30, to control current flow through the PCM cell 25 as it is being programmed.
The electrical characteristics of the PCM cell 25 of FIG. 2 is governed according to known relations:
      Icell    =                  1                              R            0                    ⁢          β                    ⁢              sinh        ⁡                  (                                    V              a                        ⁢            β                    )                          β    =                  q        ⁢                                  ⁢        Δ        ⁢                                  ⁢        z                    kT        ⁢                                  ⁢        2        ⁢                                  ⁢                  u          a                                R      0        =                            kT          ⁢                                          ⁢                      τ            0                    ⁢                      u            a                                                q            2                    ⁢                      AN            T                    ⁢          Δ          ⁢                                          ⁢                      z            2                              ⁢              ⅇ                  (                                    E              c                        -                                          E                F                            ⁢                              /                            ⁢              kT                                )                    where R0 is the low-field resistance value; Va is the applied voltage; β is a sub-threshold slope; q is an elementary charge; Δz is an average distance between two traps; k is the. Boltzmann constant; T is the temperature; and ua is the amorphous thickness; NT is a measure of the total effective trap density (a material property of the PCM cell); and the quantity EC−EF is the distance between conduction band to Fermi level (a material property of the PCM cell). Thus, it is clear that current is an exponential function of supply voltage (Va) and, further, that drift is mainly due to exponential term (EC−EF) and total effective trap density NT which vary with time.
Further, known in the industry for programming a PCM memory cell is an iterative technique implemented for adaptively controlling the amplitude of each programming pulse in a sequence of write-verify steps. That is, in a prior art methodology, to achieve multiple resistance levels in a PCM cell, there is typically implemented a programmed algorithm to provide a current pulse used to program the (desired) resistance value for a PCM bit.
FIG. 3 depicts a known implementation of an iterative write system and methodology implemented for adaptively controlling the amplitude of each programming pulse in a write-verify sequence 50. In the write-verify method, the voltage at the wordline is first SET/RESET by application of a pulse 52 to place the cell in an initial state and, with the bitline terminal held at a constant voltage, a next pulse 54a is injected at the WL terminal 32 that is immediately followed by a read operation 55 for reading in the programmed PCM cell value resulting from the application of signal 54a injected at the wordline terminal. Although not shown in FIG. 3, the read value is evaluated according to a programmed reference parameter value, e.g., a programmed reference resistance state (Rref), and the calculated difference (e.g., error) is processed and fedback to a signal generator to provide a next pulse value shown as 54b for application to the WL terminal 32 immediately followed by a read operation 55 for reading in the programmed PCM cell value resulting from the application of signal 54b injected at the wordline terminal. If, as evaluated by processing after a read operation 55, the intended programmed reference resistance state (Rref) is still not achieved, then, based on an error difference, further steps may be employed to apply a next calculated WL pulse 54c for injection at the WL terminal 32 immediately followed by the read operation 55 for reading in the programmed PCM cell value resulting from the application of signal 54c and verifying whether the programmed resistance value had been achieved. The write-verify iterative process continues executing these steps until the programmed target (Rref) parameter value, e.g., resistance, for that cell (or bit) has been reached.
It is understood that, in the embodiment depicted in FIG. 3, the pulse voltages 54a, 54b, etc., can be applied to the PCM cell WL terminal 32 (while keeping the voltage at BL terminal 28 constant); or the pulse voltages 54a, 54b, etc., can be applied to the PCM BL terminal 28 while keeping voltage at the WL terminal 32 constant. In either application, for each iteration, the state of the memory cell is always initialized, making it highest R (e.g., fully RESET the cell) or making it lowest R (e.g., fully SET the cell), then perform iterative programming-verify operation.
Thus, in view of FIG. 3, Phase Change Memory resistance can be programmed into different resistance states. For a collection of cells, process induced variations cause distributions of resistance for a target resistance level. That is, the characterized different amorphous volume and different trap density/distributions in amorphous material further results in different drift behavior of the PCM cells and broadening of distributions. The broadened distribution may cause overlap between neighboring levels, leading to cell failures.
One basic requirement for multiple bit storage in a semiconductor memory cell is to have the spectrum of the physical or electrical parameter variation, e.g., PCM cell resistance, to accommodate multiple non-overlapping bands of values. As shown in FIG. 1, the number of bands required for an n-bit cell is 2n. A 2-bit cell needs 4 bands, a 3-bit cell needs 8 bands, and so forth. Thus, the available spectrum of a physical or electrical parameter in a semiconductor memory cell is typically the limiting factor for multiple bit memory storage.
FIG. 11A shows a plot 500 of an example distribution of programmed (resistive) states in programmed multi-bit memory structures. For example, programmed resistance states 501, 502, 503 and 504 are shown depicting an original resistance distribution before exhibiting a drift phenomenon where the resistivity of the amorphous phase increases with time (drift). As a result of structural relaxation, the programmed resistance states experience drift over time as shown as corresponding distributions after drift shown as distributions 501′, 502′, 503′ and 504′. Drift spans a broad time-scale—from ns to the limit of observation time. Drift is typically modeled by the equation empirically:
      R    ⁡          (      t      )        =                    R        0            ⁡              (                  t                      t            0                          )              v  where the drift exponent (v) is proportional to the volume of the amorphous material in the active region of a PCM cell. The drift exponent also varies with the trap configuration and density within the amorphous volume. Drift also has temperature dependency. As drift is a stochastic phenomenon—it can be treated as noise. It adversely affects the reliability of stored levels in multilevel-cell PCM, leading to operational failures of the cell. For instance, drift phenomena may cause overlap of different resistance states 502, 503 as shown as resulting resistive state distribution 502′ overlapping with resulting resistive state distribution 503′ as shown in FIG. 11A that may result in operational failure of a memory cell.
FIG. 4 shows a plot 70 depicting an example programmed voltage curve 71 applied to the PCM cell and the resulting PCM cell Resistance values 73 as a function of the applied voltages 78. As shown in FIG. 4, the plot of the curve 71 shows, in the example, two adaptive write-verify iterations 74 and 75 (at k=2) with each iteration applying a modified current (voltage) required to minimize an error and achieve the programmed resistance value in the example PCM cell (RREF). In the technique as shown in FIG. 4, there is provided the ability to adaptively control the amplitude of each programming pulse in a sequence of write-verify steps. In the control, utilization of the left slope portion 76 of curve includes a Low voltage regime that ultimately uses lower power consumption, and exhibiting higher cell endurance; however, this only enables one directional programming. As a consequence, the current techniques would requires re-initialization if undershoot. Utilization of the right slope portion 77 of curve 71 facilitates two directional programming which can avoid having to implement re-initializations; and, further can operate in a high voltage regime (leading to higher power consumption, and compromised cell endurance).
Even programming cell into the same resistance at particular read voltage based on either left slope or right slope or both, the amorphous thickness should be the same. Any characterized different amorphous thickness indicated different trap density/distributions in amorphous volume. The different trap density/distributions results in different drift behavior of the PCM cells.
In the current iterative write-verify techniques, a read operation is performed to verify cell programming. Typically, in such technique, a feedback is utilized in the form of a sensing circuit for use in sensing the programmed (resistive) state of the PCM cell. Typically, this sensing circuit implements an resistive-capacitive (RC) sensing scheme to effectively sense the time it takes for a floating bitline voltage level to decay to a pre-determined (e.g., reference) voltage value corresponding to the intended (programmed) PCM cell resistance value to ensure the intended resistance value has been achieved (after programming). FIG. 5 depicts a RC-based sensing circuit 20, used to sense the resistive state (R) of the programmed PCM cell 25. As shown in FIG. 5, the bitline is modeled as a capacitive load and the voltage of the floating bit line, VBL(t), at the PCM cell BL terminal 28 is measured.
As a consequence of programmed PCM cell behavior, different resistance levels result in different RC decay speed. Resistance levels can be differentiated by sensing various floating voltage delays on BL's according to RC time constant. That is, from an initial voltage level, e.g., applied during a pre-charge stage in which an initial (e.g., pre-charge) voltage VBL(0) is present on the bitline, after time t=0, the bitline voltage is measured as a function of time, (VBL(t)), such thatVBL(t)=VBL(0)exp(−t /RC)  2)where VBL(t) is the sensed bitline voltage of a floating bitline conductor as a function of time, and VBL(0) is a pre-charged bitline voltage present at time t=0. Different resistance levels i may be sensed according to formulae:VBLi(t)=VBL(0)exp(−t/R0iC); and,t=R0iC*(log VBL(0)−log VBLi(t))where i is a resistance level (e.g., i˜1, 2, . . . 16 for a 4-bit MLC PCM cell) and R=R0i, where R0i is the programmed resistance value for the level i. Thus, the a floating VBLi(t) level associated with the intended resistance R0i should decay according to a known time t to achieve a particular reference voltage VBL value corresponding to the intended resistance R0i value. Although the measured time to achieve that particular reference voltage VBL value represents cell states, it does not indicate the same amorphous material properties (i.e., same trap density/distribution, etc.). Therefore, the programmed cell may be very susceptible in the future to (resistance) drift migration.
It would be highly desirable to provide an improved drift mitigation technique that minimizes drift during programming and improves memory reliability of programmed PCM cells.
Further, as an effort to reduce drift migration prevalent, an efficient sensing circuit is needed for determining whether the phase change memory cell is programmed into correct or desired values after the programming and less sensitive to drift in the future.